New Product SiZ920DT Vishay Siliconix Dual N-Channel 30 V (D-S) MOSFETs FEATURES PRODUCT SUMMARY TrenchFET Power MOSFETs V (V) R ( ) (Max.) I (A) Q (Typ.) DS DS(on) D g 100 % R and UIS Tested g a 0.0071 at V = 10 V GS 40 Material categorization: Channel-1 30 10.5 nC a For definitions of compliance please see 0.0089 at V = 4.5 V GS 40 www.vishay.com/doc 99912 a 0.0030 at V = 10 V GS 40 Channel-2 30 29 nC a APPLICATIONS 0.0035 at V = 4.5 V GS 40 CPU Core Power D 1 PowerPAIR 6 x 5 Computer Peripherals Pin 1 G 1 POL 5 mm 1 D 1 Synchronous Buck Converter G 2 1 D1 3 D D 1 1 N-Channel 1 4 MOSFET G 2 S /D 1 2 S /D 1 2 Pin 9 8 S 2 7 6 mm 6 G 2 5 N-Channel 2 Ordering Information: MOSFET S 2 SiZ920DT-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A Parameter Symbol Channel-1Channel-2Unit V 30 Drain-Source Voltage DS V V 20 Gate-Source Voltage GS a a T = 25 C 40 40 C a a T = 70 C 40 40 C Continuous Drain Current (T = 150 C) I D J b, c b, c T = 25 C A 22 32 b, c b, c T = 70 C 17 26 A A I Pulsed Drain Current (t = 300 s) 70 120 DM a a T = 25 C 28 C 28 Continuous Source Drain Diode Current I S b, c b, c T = 25 C 3.6 4.3 A I Single Pulse Avalanche Current 25 40 AS L = 0.1 mH E Single Pulse Avalanche Energy 31 80 mJ AS T = 25 C 39 100 C T = 70 C 25 64 C Maximum Power Dissipation P W D b, c b, c T = 25 C A 4.3 5.2 b, c b, c T = 70 C 2.8 3.3 A T , T Operating Junction and Storage Temperature Range - 55 to 150 J stg C d, e Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS Channel-1 Channel-2 Parameter Symbol Typ. Max. Typ. Max. Unit b, f t 10 s R 23 29 19 24 Maximum Junction-to-Ambient thJA C/W R Maximum Junction-to-Case (Drain) Steady State 2.5 3.2 1 1.25 thJC Notes: a. Package limited - T = 25 C. C b. Surface mounted on 1 x 1 FR4 board. c. t = 10 s. d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 65 C/W for channel-1 and 55 C/W for channel-2. Document Number: 63916 For technical questions, contact: pmostechsupport vishay.com www.vishay.com S12-0975-Rev. A, 30-Apr-12 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000New Product SiZ920DT Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J Parameter Symbol Test Conditions Min. Typ.Max.Unit Static V = 0 V, I = 250 A Ch-1 30 GS D V Drain-Source Breakdown Voltage V DS V = 0 V, I = 250 A Ch-2 30 GS D I = 250 A Ch-1 34 D V Temperature Coefficient V /T DS DS J I = 250 A Ch-2 31 D mV/C I = 250 A Ch-1 - 5.2 D V Temperature Coefficient V /T GS(th) GS(th) J I = 250 A Ch-2 - 6.1 D V = V , I = 250 A Ch-1 1.2 2.5 DS GS D V Gate Threshold Voltage V GS(th) V = V , I = 250 A Ch-2 1 2.2 DS GS D Ch-1 100 I V = 0 V, V = 20 V Gate Source Leakage nA GSS DS GS Ch-2 100 V = 30 V, V = 0 V Ch-1 1 DS GS V = 30 V, V = 0 V Ch-2 1 DS GS I Zero Gate Voltage Drain Current A DSS V = 30 V, V = 0 V, T = 55 C Ch-1 5 DS GS J V = 30 V, V = 0 V, T = 55 C Ch-2 5 DS GS J V 5 V, V = 10 V Ch-1 20 DS GS b I A On-State Drain Current D(on) V 5 V, V = 10 V Ch-2 25 DS GS V = 10 V, I = 18.9 A Ch-1 0.0059 0.0071 GS D V = 10 V, I = 20 A Ch-2 0.0025 0.0030 GS D b R Drain-Source On-State Resistance DS(on) V = 4.5 V, I = 16.9 A Ch-1 0.0074 0.0089 GS D V = 4.5 V, I = 20 A Ch-2 0.0029 0.0035 GS D V = 10 V, I = 18.9 A Ch-1 66 DS D b g S Forward Transconductance fs V = 10 V, I = 20 A Ch-2 140 DS D a Dynamic Ch-1 1260 C Input Capacitance iss Channel-1 Ch-2 3600 V = 15 V, V = 0 V, f = 1 MHz DS GS Ch-1 260 C Output Capacitance pF oss Ch-2 660 Channel-2 Ch-1 115 V = 15 V, V = 0 V, f = 1 MHz DS GS C Reverse Transfer Capacitance rss Ch-2 305 V = 15 V, V = 10 V, I = 18.9 A Ch-1 22.3 35 DS GS D V = 15 V, V = 10 V, I = 20 A Ch-2 60 110 DS GS D Total Gate Charge Q g Ch-1 10.5 16 Channel-1 Ch-2 29 51 nC V = 15 V, V = 4.5 V, I = 18.9 A DS GS D Ch-1 5.1 Q Gate-Source Charge gs Ch-2 10 Channel-2 Ch-1 2.8 V = 15 V, V = 4.5 V, I = 20 A DS GS D Q Gate-Drain Charge gd Ch-2 9.5 Ch-1 0.3 1.6 3.2 R Gate Resistance f = 1 MHz g Ch-2 0.1 0.6 1.2 Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test pulse width 300 s, duty cycle 2 %. www.vishay.com For technical questions, contact: pmostechsupport vishay.com Document Number: 63916 2 S12-0975-Rev. A, 30-Apr-12 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000