6 mm6 mm SiZ926DT www.vishay.com Vishay Siliconix Dual N-Channel 25 V (D-S) MOSFETs FEATURES PowerPAIR 6 x 5 G 2 S 2 TrenchFET Gen IV power MOSFETs 8 S 2 7 S 2 6 100 % R and UIS tested g 5 S /D 1 2 Optimized Q /Q ratio improves switching gs gs (Pin 9) characteristics D 1 1 Material categorization: 2 G 1 3 D for definitions of compliance please se e 1 4 11 D 1 www.vishay.com/doc 99912 D 1 Top View Bottom View D APPLICATIONS 1 PRODUCT SUMMARY CPU core power CHANNEL-1 CHANNEL-2 G 1 Computer / server peripherals V (V) 25 25 DS N-Channel 1 S /D R max. ( ) at V = 10 V 0.00480 0.00220 1 2 DS(on) GS POL MOSFET R max. ( ) at V = 4.5 V 0.00790 0.00335 DS(on) GS Synchronous buck converter Q typ. (nC) 5.9 12.5 g G 2 Telecom DC/DC a, g I (A) 40 60 N-Channel 2 D MOSFET S Configuration Dual 2 ORDERING INFORMATION Package PowerPAIR 6 x 5 Lead (Pb)-free and halogen-free SiZ926DT-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL CHANNEL-1 CHANNEL-2 UNIT Drain-source voltage V 25 25 DS V Gate-source voltage V +16, -12 +16, -12 GS a a T = 25 C 40 60 C a a T = 70 C 40 60 C Continuous drain current (T = 150 C) I J D b, c b, c T = 25 C 22 37 A b, c b, c T = 70 C 17.5 30 A A Pulsed drain current (100 s pulse width) I 100 170 DM T = 25 C 16.8 33.6 C Continuous source drain diode current I S b, c b, c T = 25 C 3.2 4 A Single pulse avalanche current I 15 28 AS L = 0.1 mH Single pulse avalanche energy E 11 39 mJ AS T = 25 C 20.2 40 C T = 70 C 12.9 25.8 C Maximum power dissipation P W D b, c b, c T = 25 C 3.8 4.8 A b, c b, c T = 70 C 2.4 3.1 A Operating junction and storage temperature range T , T -55 to +150 J stg C d Soldering recommendations (peak temperature) 260 THERMAL RESISTANCE RATINGS CHANNEL-1 CHANNEL-2 PARAMETER SYMBOL UNIT TYP. MAX. TYP. MAX. b, f Maximum junction-to-ambient t 10 s R 26 33 21 26 thJA C/W Maximum junction-to-case (drain) Steady state R 4.7 6.2 2.5 3.1 thJC Notes a. Package limited b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PowerPAIR is a leadless package. The end of the lead terminal is exposed coppe r (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components f. Maximum under steady state conditions is 68 C/W for channel-1 and 57 C/W for channel-2 g. T = 25 C C S19-0939-Rev. C, 11-Nov-2019 Document Number: 68127 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 5 mm SiZ926DT www.vishay.com Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static V = 0 V, I = 250 A Ch-1 25 - - GS D Drain-source breakdown voltage V V DS V = 0 V, I = 250 A Ch-2 25 - - GS D I = 250 A Ch-1 - 19 - D V Temperature coefficient V /T DS DS J I = 250 A Ch-2 - 15 - D mV/C I = 250 A Ch-1 - 4.9 - D V Temperature coefficient V /T GS(th) GS(th) J I = 250 A Ch-2 - 4.6 - D V = V , I = 250 A Ch-1 1.1 - 2.2 DS GS D Gate threshold voltage V V GS(th) V = V , I = 250 A Ch-2 1.1 - 2.4 DS GS D Ch-1 - - 100 Gate source leakage I V = 0 V, V = +16 V, -12 V nA GSS DS GS Ch-2 - - 100 V = 25 V, V = 0 V Ch-1 - - 1 DS GS V = 25 V, V = 0 V Ch-2 - - 1 DS GS Zero gate voltage drain current I A DSS V = 25 V, V = 0 V, T = 55 C Ch-1 - - 10 DS GS J V = 25 V, V = 0 V, T = 55 C Ch-2 - - 10 DS GS J V 5 V, V = 10 V Ch-1 20 - - DS GS b On-state drain current I A D(on) V 5 V, V = 10 V Ch-2 20 - - DS GS V = 10 V, I = 5 A Ch-1 - 0.00380 0.00480 GS D V = 10 V, I = 8 A Ch-2 - 0.00173 0.00220 GS D b Drain-source on-state resistance R DS(on) V = 4.5 V, I = 3 A Ch-1 - 0.00640 0.00790 GS D V = 4.5 V, I = 5 A Ch-2 - 0.00265 0.00335 GS D V = 10 V, I = 5 A Ch-1 - 40 - GS D b Forward transconductance g S fs V = 10 V, I = 8 A Ch-2 - 55 - GS D a Dynamic Ch-1 - 925 - Input capacitance C iss Ch-2 - 2150 - Ch-1 - 310 - Channel-1 Output capacitance C pF oss V = 10 V, V = 10 V, f = 1 MHz DS GS Ch-2 - 800 - Ch-1 - 52 - Channel-2 Reverse transfer capacitance C rss V = 10 V, V = 10 V, f = 1 MHz Ch-2 - 100 - DS GS Ch-1 - 0.056 0.115 C /C ratio rss iss Ch-2 - 0.047 0.095 V = 10 V, V = 10 V, I = 5 A Ch-1 - 12.5 19 DS GS D V = 10 V, V = 10 V, I = 8 A Ch-2 - 27 41 DS GS D Total gate charge Q g V = 10 V, V = 4.5 V, I = 5 A Ch-1 - 5.9 8.9 DS GS D V = 10 V, V = 4.5 V, I = 8 A Ch-2 - 12.5 19 DS GS D Ch-1 - 2.5 - Channel-1 Gate-source charge Q nC gs V = 10 V, V = 4.5 V, I = 5 A DS GS D Ch-2 - 5.4 - Ch-1 - 1.2 - Channel-2 Gate-drain charge Q gd V = 10 V, V = 4.5 V, I = 8 A DS GS D Ch-2 - 2.1 - Ch-1 - 5 - Output charge Q V = 10 V, V = 0 V oss DS GS Ch-2 - 13 - Ch-1 0.18 0.92 1.9 Gate resistance R f = 1 MHz g Ch-2 0.12 0.6 1.2 S19-0939-Rev. C, 11-Nov-2019 Document Number: 68127 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000