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The switch node has been internally connected to DS(on) GS D enable easy placement and routing of synchronous buck Q2: N-Channel converters. The control MOSFET (Q1) and synchronous Max r = 2.1 m at V = 4.5 V, I = 24 A DS(on) GS D TM SyncFET (Q2) have been designed to provide optimal power Low inductance packaging shortens rise/fall times, resulting in efficiency. lower switching losses Applications MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing Computing RoHS Compliant Communications General Purpose Point of Load Pin 1 V+ Pin 1 LS GND V+ PAD9 V+ HSG V+ HSG GND (HSD V+(HSD) GND SW SW LSG LSG (LSS HSG SW SW SW GND SW GND SW SW PAD10 GND(LSS) GND GND SW SW Bottom Top 3.3 mm x 3.3 mm MOSFET Maximum Ratings T = 25 C unless otherwise noted A Symbol Parameter Q1 Q2 Units V Drain to Source Voltage 25 25 V DS V Gate to Source Voltage 12 12 V GS Drain Current -Continuous (Package limited) T = 25 C 20 60 C 1a 1b I -Continuous T = 25 C 13 27 A D A -Pulsed 40 120 E Single Pulse Avalanche Energy (Note 3) 21 97 mJ AS 1a 1b Power Dissipation for Single Operation T = 25 C 1.6 2.0 A P W D 1c 1d Power Dissipation for Single Operation T = 25 C 0.8 0.9 A T , T Operating and Storage Junction Temperature Range -55 to +150 C J STG Thermal Characteristics 1a 1b R Thermal Resistance, Junction to Ambient 77 63 JA 1c 1d R Thermal Resistance, Junction to Ambient 151 135 C/W JA R Thermal Resistance, Junction to Case 5.0 3.5 JC Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity 13OD/15OD FDPC8011S Power Clip 33 13 12 mm 3000 units 1 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FDPC8011S Rev.C6