TSM2318 Taiwan Semiconductor N-Channel Power MOSFET 40V, 3.9A, 45m FEATURES KEY PERFORMANCE PARAMETERS Advance Trench Process Technology PARAMETER VALUE UNIT High density cell design for Ultra Low On-resistance V 40 V DS Pb-free plating V = 10V 45 GS Compliant to RoHS Directive 2011/65/EU and in R (max) m DS(on) V = 4.5V 62.5 GS accordance to WEE2002/96/EC Halogen-free according to IEC 61249-2-21 definition Qg 10 nC APPLICATION Load Switch Stepper Motors SOT-23 Notes: MSL 3 (Moisture Sensitivity Level) per J-STD-020 ABSOLUTE MAXIMUM RATINGS (T = 25C unless otherwise noted) A PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V 40 V DS Gate-Source Voltage V 20 V GS (Note 1) Continuous Drain Current I 3.9 A D (Note 2) Pulsed Drain Current I 16 A DM Total Power Dissipation T = 25C P 1.25 W A DTOT Operating Junction and Storage Temperature Range T , T - 55 to +150 C J STG THERMAL PERFORMANCE PARAMETER SYMBOL LIMIT UNIT Junction to Case Thermal Resistance R 50 C/W JC Junction to Ambient Thermal Resistance R 100 C/W JA Notes: R is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined JA at the solder mounting surface of the drain pins. R is guaranteed by design while R is determined by the users board JA CA design. R shown below for single device operation on FR-4 PCB with minimum recommended footprint in still air. JA Document Number: DS P0000057 1 Version: C15 TSM2318 Taiwan Semiconductor ELECTRICAL SPECIFICATIONS (T = 25C unless otherwise noted) A PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNIT (Note 3) Static Drain-Source Breakdown Voltage V = 0V, I = 250A BV 40 -- -- GS D DSS V Gate Threshold Voltage V = V , I = 250A V 1 -- 3 V DS GS D GS(TH) Gate Body Leakage V = 20V, V = 0V I -- -- 100 nA GS DS GSS Zero Gate Voltage Drain Current V = 32V, V = 0V I -- -- 1.0 A DS GS DSS V = 10V, I = 3.9A -- 36 45 GS D Drain-Source On-State Resistance R m DS(on) V = 4.5V, I = 3.5A 50 62.5 GS D (Note 4) Dynamic Total Gate Charge Q -- 10 -- g V = 20V, I = 3.9A, DS D Gate-Source Charge Q -- 1.6 -- nC gs V = 10V GS Gate-Drain Charge Q -- 2.1 -- gd Input Capacitance C -- 540 -- iss V = 20V, V = 0V, DS GS Output Capacitance C -- 80 -- pF oss f = 1.0MHz Reverse Transfer Capacitance C -- 45 -- rss (Note 5) Switching Turn-On Delay Time t -- 5 -- d(on) V = 20V, R = 20, DD L Turn-On Rise Time t -- 12 -- r I = 1A, V = 10V, ns D GEN Turn-Off Delay Time t -- 20 -- d(off) R = 6 G Turn-Off Fall Time t -- 15 -- f (Note 3) Source-Drain Diode Forward On Voltage I = 1.25A, V = 0V V -- 0.8 1.2 V S GS SD Notes: 1. Current limited by package 2. Pulse width limited by the maximum junction temperature 3. Pulse test: PW 300s, duty cycle 2% 4. For DESIGN AID ONLY, not subject to production testing. 5. Switching time is essentially independent of operating temperature. Document Number: DS P0000057 2 Version: C15