Si5486DU Vishay Siliconix N-Channel 20-V (D-S) MOSFET FEATURES PRODUCT SUMMARY TrenchFET Power MOSFET a New Thermally Enhanced PowerPAK V (V) R () Q (Typ.) I (A) DS DS(on) g D ChipFET Package 0.015 at V = 4.5 V 12 GS - Small Footprint Area - Low On-Resistance 0.017 at V = 2.5 V 12 20 21 nC GS - Thin 0.8 mm Profile 0.021 at V = 1.8 V 12 GS Material categorization: For definitions of compliance please see www.vishay.com/doc 99912 PowerPAK ChipFET Single APPLICATIONS Load Switch, PA Switch, and for Portable Applications 1 2 Point-of-Load D 3 D D D 4 D D 8 G D 7 S Marking Code 6 S 5 AG XXX G Lot Traceability and Date Code Bottom View Part Code S Ordering Information: Si5486DU-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A Parameter Symbol Limit Unit Drain-Source Voltage V 20 DS V V 8 Gate-Source Voltage GS a T = 25 C 12 C a T = 70 C 12 C Continuous Drain Current (T = 150 C) I J D b, c T = 25 C A 11.6 b, c T = 70 C A 9.3 A Pulsed Drain Current I 40 DM a T = 25 C C 12 Continuous Source-Drain Diode Current I S b, c T = 25 C 2.6 A T = 25 C 31 C T = 70 C 20 C Maximum Power Dissipation P W D b, c T = 25 C 3.1 A b, c T = 70 C 2 A T , T - 55 to 150 Operating Junction and Storage Temperature Range J stg C d, e 260 Soldering Recommendations (Peak Temperature) THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit b, f t 5 s R 34 40 Maximum Junction-to-Ambient thJA C/W Maximum Junction-to-Case (Drain) Steady State R 34 thJC Notes: a. Package limited. b. Surface mounted on 1 x 1 FR4 board. c. t = 5 s. d. See solder profile (www.vishay.com/doc 73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 90 C/W. Document Number: 73783 www.vishay.com For technical questions, contact: pmostechsupport vishay.com S13-0194-Rev. C, 28-Jan-13 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000Si5486DU Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static V V = 0 V, I = 250 A Drain-Source Breakdown Voltage 20 V DS GS D V Temperature Coefficient V /T 21 DS DS J I = 250 A mV/C D V Temperature Coefficient V /T - 3.4 GS(th) GS(th) J V V = V , I = 250 A V Gate-Source Threshold Voltage 0.4 1 GS(th) DS GS D I V = 0 V, V = 8 V Gate-Source Leakage 100 nA GSS DS GS V = 20 V, V = 0 V 1 DS GS Zero Gate Voltage Drain Current I A DSS V = 20 V, V = 0 V, T = 55 C 10 DS GS J a I V 5 V, V = 4.5 V A 40 On-State Drain Current D(on) DS GS V 4.5 V, I = 7.7 A 0.012 0.015 GS D a R V 2.5 V, I = 7.3 A 0.014 0.017 Drain-Source On-State Resistance DS(on) GS D V 1.8 V, I = 4.8 A 0.017 0.021 GS D a g V = 10 V, I = 7.7 A 46 S Forward Transconductance fs DS D b Dynamic C Input Capacitance 2100 iss C V = 10 V, V = 0 V, f = 1 MHz Output Capacitance 310 pF oss DS GS C Reverse Transfer Capacitance 180 rss V = 10 V, V = 8 V, I = 9.3 A 36 54 DS GS D Total Gate Charge Q g 21 32 nC Q Gate-Source Charge 3.3 gs V = 10 V, V = 4.5 V, I = 9.3 A DS GS D Gate-Drain Charge Q 3.1 gd R f = 1 MHz Gate Resistance 5 g Turn-on Delay Time t 10 15 d(on) V = 10 V, R = 1.1 t Rise Time DD L 15 25 r I 9.3 A, V = 4.5 V, R = 1 D GEN g Turn-Off Delay Time t 50 75 d(off) t Fall Time 15 25 f ns Turn-On Delay Time t 715 d(on) V = 10 V, R = 1.1 t Rise Time DD L 15 25 r I 9.3 A, V = 10 V, R = 1 D GEN g Turn-Off Delay Time t 55 85 d(off) t Fall Time 10 15 f Drain-Source Body Diode Characteristics I T = 25 C Continuous Source-Drain Diode Current 12 S C A I Pulse Diode Forward Current 40 SM V I = 9.1 A, V = 0 V Body Diode Voltage 0.8 1.2 V SD S GS t Body Diode Reverse Recovery Time 30 60 ns rr Q Body Diode Reverse Recovery Charge 17 30 nC rr I = 9.3 A, dI/dt = 100 A/s, T = 25 C F J Reverse Recovery Fall Time t 12 a ns t Reverse Recovery Rise Time 18 b Notes: a. Pulse test pulse width 300 s, duty cycle 2 % b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 73783 For technical questions, contact: pmostechsupport vishay.com 2 S13-0194-Rev. C, 28-Jan-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000