New Product Si7120ADN Vishay Siliconix N-Channel 60 V (D-S) MOSFET FEATURES PRODUCT SUMMARY Halogen-free According to IEC 61249-2-21 V (V) R ()I (A) DS DS(on) D Definition 0.021 at V = 10 V 9.5 GS TrenchFET Power MOSFET 60 0.031 at V = 4.5 V 7.9 GS 100 % R Tested g 100 % UIS Tested Compliant to RoHS Directive 2002/95/EC PowerPAK 1212-8 APPLICATIONS Primary Side Switch Synchronous Rectification S 3.30 mm 3.30 mm D 1 S 2 S 3 G 4 D 8 D G 7 D 6 D 5 BottomView S Ordering Information: Si7120ADN-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS T = 25 C, unless otherwise noted A Parameter Symbol 10 s Steady State Unit Drain-Source Voltage V 60 DS V Gate-Source Voltage V 20 GS T = 25 C 9.5 6.0 A Continuous Drain Current (T = 150 C) I J D T = 70 C 7.6 4.8 A Pulsed Drain Current I 40 A DM a I 3.2 1.3 Continuous Source Current (Diode Conduction) S Single Avalanche Current I 22 AS L = 0.1 mH Single Avalanche Energy E 24 mJ AS T = 25 C 3.8 1.5 A a Maximum Power Dissipation P W D T = 70 C 2.4 1.0 A Operating Junction and Storage Temperature Range T , T - 55 to 150 J stg C b, c Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit t 10 s 26 33 a Maximum Junction-to-Ambient R thJA Steady State 65 81 C/W Maximum Junction-to-Case (Drain) Steady State R 1.9 2.4 thJC Notes: a. Surface mounted on 1 x 1 FR4 board. b. See solder profile (www.vishay.com/ppg 73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. c. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: 72959 www.vishay.com S10-1041-Rev. A, 03-May-10 1New Product Si7120ADN Vishay Siliconix SPECIFICATIONS T = 25 C, unless otherwise noted J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static Gate Threshold Voltage V V = V , I = 250 A 1.5 2.5 3.0 V GS(th) DS GS D Gate Body Leakage I V = 0 V, V = 20 V 100 nA GSS DS GS V = 60 V, V = 0 V 1 DS GS Zero Gate Voltage Drain Current I A DSS V = 60 V, V = 0 V, T = 55 C 5 DS GS J a On-State Drain Current I V 5 V, V = 10 V 30 A D(on) DS GS V = 10 V, I = 9.5 A 0.0175 0.021 GS D a Drain-Source On-State Resistance R DS(on) V = 4.5 V, I = 7.9 A 0.025 0.031 GS D a Forward Transconductance g V = 15 V, I = 9.5 A 35 S fs DS D a Diode Forward Voltage V I = 3.2 A, V = 0 V 0.78 1.2 V SD S GS b Dynamic Total Gate Charge Q 30 45 g Gate-Source Charge Q 6.9V = 10 V, V = 10 V, I = 9.5 A nC gs DS GS D Gate-Drain Charge Q 5.8 gd Gate Resistance R 0.65 1.3 1.95 g Turn-On Delay Time t 14 25 d(on) Rise Time t 1220 V = 30 V, R = 30 r DD L I 1 A, V = 10 V, R = 6 Turn-Off Delay Time t 50D GEN g 80 ns d(off) Fall Time t 12 20 f Source-Drain Reverse Recovery Time t I = 3.2 A, dI/dt = 100 A/s 60 100 rr F Notes: a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 72959 2 S10-1041-Rev. A, 03-May-10