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This literature is subject to all applicable copyright laws and is not for resale in any manner.FDG6318PZ January 2003 FDG6318PZ Dual P-Channel, Digital FET General Description Features These dual P-Channel logic level enhancement mode -0.5A, -20V. r = 780m ( Max) V = -4.5 V DS(ON) GS MOSFET are produced using Fairchild Semiconductors r = 1200m ( Max) V = -2.5 V DS(ON) GS especially tailored to minimize on-state resistance. This Very low level gate drive requirements allowing direct device has been designed especially for bipolar digital transistors and small signal MOSFETS operation in 3V circuits (V < 1.5V). GS(TH) Gate-Source Zener for ESD ruggedness (>1.4kV Human Applications Body Model). Battery management Compact industry standard SC-70-6 surface mount package. S G S D 1or 4 6or 3 D G 2or 5 5or 2 G D G Pin 1 S D 3or 6 4or 1 S SC70-6 The pinouts are symmetrical pin1 and pin 4 are interchangeable. MOSFET Maximum Ratings T =25C unless otherwise noted A Symbol Parameter Ratings Units V Drain to Source Voltage -20 V DSS V Gate to Source Voltage 12 V GS Drain Current o -0.5 A Continuous (T = 25 C, V = - 4.5V) C GS I D o Continuous (T = 100 C, V = - 2.5V) -0.3 A C GS Pulsed Figure 4 Power dissipation 0.3 W P D o Derate above 25C 2.4 mW/ C o T , T Operating and Storage Temperature -55 to 150 C J STG Electrostatic Discharge Rating MIL-STD-883D ESD 1.4 kV Human Body Model ( 100pF / 1500 ) Thermal Characteristics o R Thermal Resistance Junction to Ambient (Note 1) 415 C/W JA Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity .68 FDG6318PZ SC70-6 7 8 mm 3000 2003 Fairchild Semiconductor Corporation FDG6318PZ Rev. B