TSM3401 Taiwan Semiconductor P-Channel Power MOSFET -30V, -3A, 60m KEY PERFORMANCE PARAMETERS Features PARAMETER VALUE UNIT Advance Trench Process Technology V -30 V DS High Density Cell Design for Ultra Low On- V = -10V resistance GS 60 R (max) m DS(on) Pb-free plating V = -4.5V 90 GS RoHS compliant Q 9.52 nC g Halogen-free package Application Load Switch PA Switch SOT-23 Notes: Moisture sensitivity level: level 3. Per J-STD-020 ABSOLUTE MAXIMUM RATINGS (T = 25C unless otherwise noted) A PARAMETER SYMBOL LIMIT UNIT -30 Drain-Source Voltage V V DS Gate-Source Voltage V 20 V GS (Note 1) -3 Continuous Drain Current T = 25C I A A D (Note 2) Pulsed Drain Current I -10 A DM Continuous Source Current (Diode Conduction) I -1.9 A S T = 25C 1.25 A Total Power Dissipation P W DTOT T = 70C 0.8 A Operating Junction and Storage Temperature Range T , T - 55 to +150 C J STG THERMAL PERFORMANCE PARAMETER SYMBOL LIMIT UNIT Junction to Case Thermal Resistance R 75 C/W JC Junction to Ambient Thermal Resistance R 100 C/W JA Notes: R is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined JA at the solder mounting surface of the drain pins. R is guaranteed by design while R is determined by the users board JA CA design. R shown below for single device operation on FR-4 PCB in still air. JA Document Number: DS P0000072 1 Version: D15 TSM3401 Taiwan Semiconductor ELECTRICAL SPECIFICATIONS (T = 25C unless otherwise noted) A PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNIT (Note 3) Static Drain-Source Breakdown Voltage V = 0V, I = -250A BV -30 -- -- V GS D DSS Gate Threshold Voltage V = V , I = -250A V -1.0 -1.5 -3.0 DS GS D GS(TH) V Gate Body Leakage V = 20V, V = 0V I -- -- 100 GS DS GSS nA Zero Gate Voltage Drain Current V = -24V, V = 0V I -- -- -1 A DS GS DSS On-State Drain Current V = -5V, V = -10V I -6 -- -- A DS GS D(ON) V = -10V, I = -3A -- 50 60 GS D Drain-Source On-State Resistance R m DS(ON) -- V = -4.5V, I = -2A 75 90 GS D V = -15V, I = -5A 4 7 -- Forward Transconductance DS D g S fs (Note 4) Dynamic Total Gate Charge Q -- 9.52 -- g V = -15V, I = -3A, DS D Gate-Source Charge Q -- 3.43 -- nC gs V = -10V GS Gate-Drain Charge Q -- 1.71 -- gd Input Capacitance C -- 551.57 -- iss V = -15V, V = 0V, DS GS Output Capacitance C -- 90.96 -- oss pF f = 1.0MHz Reverse Transfer Capacitance C 60.79 rss (Note 5) Switching Turn-On Delay Time t -- -- 10.8 d(on) V = -15V, DD Turn-On Rise Time t -- 2.33 -- r R = 6, ns GEN Turn-Off Delay Time t -- 22.53 -- d(off) I = -1A, V = -10V, D GS Turn-Off Fall Time t -- 3.87 -- f (Note 3) Source-Drain Diode Forward On Voltage -- -0.8 -1.3 V I = -1.9 A, V = 0V V S GS SD Notes: 1. Pulse width limited by the maximum junction temperature. 2. Surface Mounted on FR4 Board, t 5 sec. 3. Pulse test: PW 300s, duty cycle 2%. 4. For DESIGN AID ONLY, not subject to production testing. 5. Switching time is essentially independent of operating temperature. Document Number: DS P0000072 2 Version: D15