SiA519EDJ Vishay Siliconix N- and P-Channel 20-V (D-S) MOSFET FEATURES PRODUCT SUMMARY TrenchFET Power MOSFETs V (V) R ()I (A) Q (Typ.) DS DS(on) D g Typical ESD Protection: N-Channel 2000 V a P-Channel 1000 V 0.040 at V = 4.5 V GS 4.5 N-Channel 20 3.7 nC 100 % R Tested a 0.065 at V = 2.5 V g GS 4.5 Material categorization: a 0.090 at V = - 4.5 V - 4.5 GS For definitions of compliance please see P-Channel - 20 5.3 nC a 0.137 at V = - 2.5 V GS - 4.5 www.vishay.com/doc 99912 PowerPAK SC-70-6 Dual D S 1 2 1 S 1 2 G 1 3 D 1 D 2 G 1 Marking Code D 1 G D 2 2 6 E G X G 2 Part code 5 2.05 mm X X X 2.05 mm S 2 4 Lot Traceability and Date code D S 2 1 Ordering Information: SiA519EDJ-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET P-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A Parameter Symbol N-ChannelP-ChannelUnit V 20 - 20 Drain-Source Voltage DS V V 12 Gate-Source Voltage GS a a T = 25 C 4.5 - 4.5 C a a T = 70 C 4.5 - 4.5 C I Continuous Drain Current (T = 150 C) D J a, b, c b, c T = 25 C A 4.5 - 3.7 b, c b, c T = 70 C A 4.4 - 3 A I Pulsed Drain Current DM 15 - 15 a a T = 25 C 4.5 - 4.5 C Source Drain Current Diode Current I S b, c b, c T = 25 C 1.6 - 1.6 A T = 25 C 7.8 7.8 C T = 70 C 55 C Maximum Power Dissipation P W D b, c b, c T = 25 C 1.9 1.9 A b, c b, c T = 70 C A 1.2 1.2 T , T Operating Junction and Storage Temperature Range - 55 to 150 J stg C d, e Soldering Recommendations (Peak Temperature) 260 THERMAL RESISTANCE RATINGS N-Channel P-Channel Parameter Symbol Typ. Max. Typ. Max. Unit b, f t 5 s R 52 65 52 65 Maximum Junction-to-Ambient thJA C/W R Maximum Junction-to-Case (Drain) Steady State 12.5 16 12.5 16 thJC Notes: a. Package limited. b. Surface mounted on 1 x 1 FR4 board. c. t = 5 s. d. See solder profile (www.vishay.com/doc 73257). The PowerPAK SC-70 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 110 C/W. Document Number: 65176 For technical questions, contact: pmostechsupport vishay.com www.vishay.com S13-1890-Rev. D, 02-Sep-13 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000SiA519EDJ Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J Parameter Symbol Test Conditions Min. Typ.Max.Unit Static V = 0 V, I = 250 A N-Ch 20 GS D V Drain-Source Breakdown Voltage V DS V = 0 V, I = - 250 A P-Ch - 20 GS D I = 250 A N-Ch 23 D V Temperature Coefficient V /T DS DS J I = - 250 A P-Ch - 11 D mV/C I = 250 A N-Ch - 3.3 D V Temperature Coefficient V /T GS(th) GS(th) J I = - 250 A P-Ch 2.6 D V = V , I = 250 A N-Ch 0.6 1.4 DS GS D V Gate Threshold Voltage V GS(th) V = V , I = - 250 A P-Ch - 0.5 - 1.3 DS GS D N-Ch 0.5 V = 0 V, V = 4.5 V DS GS P-Ch 0.5 I Gate-Body Leakage GSS N-Ch 90 V = 0 V, V = 12 V DS GS P-Ch 8 A V = 20 V, V = 0 V N-Ch 1 DS GS V = - 20 V, V = 0 V P-Ch - 1 DS GS I Zero Gate Voltage Drain Current DSS V = 20 V, V = 0 V, T = 55 C N-Ch 10 DS GS J V = - 20 V, V = 0 V, T = 55 C P-Ch - 10 DS GS J V 5 V, V = 4.5 V N-Ch 10 DS GS b I A On-State Drain Current D(on) V - 5 V, V = - 4.5 V P-Ch - 10 DS GS V = 4.5 V, I = 4.2 A N-Ch 0.032 0.040 GS D V = - 4.5 V, I = - 2.9 A P-Ch 0.074 0.090 GS D b R Drain-Source On-State Resistance DS(on) V = 2.5 V, I = 3.3 A N-Ch 0.053 0.065 GS D V = - 2.5 V, I = - 2.3 A P-Ch 0.113 0.137 GS D V = 10 V, I = 4.2 A N-Ch 12 DS D b g S Forward Transconductance fs V = - 10 V, I = - 2.9 A P-Ch 7 DS D a Dynamic N-Ch 350 C Input Capacitance iss N-Channel P-Ch 340 V = 10 V, V = 0 V, f = 1 MHz DS GS N-Ch 82 C Output Capacitance pF oss P-Ch 105 P-Channel N-Ch 50 V = - 10 V, V = 0 V, f = 1 MHz DS GS C Reverse Transfer Capacitance rss P-Ch 95 V = 10 V, V = 10 V, I = 5.5 A N-Ch 7.7 12 DS GS D V = - 10 V, V = - 10 V, I = - 3.7 A P-Ch 10.5 16 DS GS D Total Gate Charge Q g N-Ch 3.7 6 N-Channel P-Ch 5.3 8 nC V = 10 V, V = 4.5 V, I = 5.5 A DS GS D N-Ch 0.85 Q Gate-Source Charge gs P-Ch 0.75 P-Channel N-Ch 0.95 V = - 10 V, V = - 4.5 V, I = - 3.7 A DS GS D Q Gate-Drain Charge gd P-Ch 2 N-Ch 0.7 3.5 7 R Gate Resistance f = 1 MHz g P-Ch 0.2 10 20 Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test pulse width 300 s, duty cycle 2 %. www.vishay.com For technical questions, contact: pmostechsupport vishay.com Document Number: 65176 2 S13-1890-Rev. D, 02-Sep-13 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000