New Product SiB441EDK Vishay Siliconix P-Channel 12-V (D-S) MOSFET FEATURES PRODUCT SUMMARY TrenchFET Power MOSFET V (V) R ( ) Max. I (A) Q (Typ.) DS DS(on) D g Thermally Enhanced PowerPAK a 0.0255 at V = - 4.5 V SC-75 Package GS - 9 - Small Footprint Area a 0.0280 at V = - 3.7 V - 9 GS - Low On-Resistance a - 12 0.0360 at V = - 2.5 V 13.4 nC GS - 9 Typical ESD Performance 2500 V a 0.0600 at V = - 1.8 V GS - 9 100 % R Tested g 0.1150 at V = - 1.5 V - 2 Material categorization: For definitions of compliance GS please see www.vishay.com/doc 99912 PowerPAK SC-75-6L-Single S APPLICATIONS Portable Devices such as Smart Phones, Tablet PCs and 1 Mobile Computing D - Battery Switch 2 D - Load Switch 3 G - Power Management G D 6 S Marking Code D 5 1.60 mm S B O X 1.60 mm 4 Part code X X X D Lot Traceability P-Channel MOSFET and Date code Ordering Information: SiB441EDK-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A Parameter Symbol LimitUnit V - 12 Drain-Source Voltage DS V Gate-Source Voltage V 8 GS a T = 25 C - 9 C a T = 70 C - 9 C Continuous Drain Current (T = 150 C) I J D b, c T = 25 C - 8.3 A b, c T = 70 C A - 6.6 A I - 40 Pulsed Drain Current (t = 300 s) DM a - 9 T = 25 C C Continuous Source-Drain Diode Current I S b, c T = 25 C - 2 A T = 25 C 13 C T = 70 C 8.4 C Maximum Power Dissipation P W D b, c T = 25 C 2.4 A b, c T = 70 C 1.6 A Operating Junction and Storage Temperature Range T , T - 55 to 150 J stg C d, e 260 Soldering Recommendations (Peak Temperature) THERMAL RESISTANCE RATINGS Parameter Symbol TypicalMaximumUnit b, f R t 5 s 41 51 Maximum Junction-to-Ambient thJA C/W R Maximum Junction-to-Case (Drain) Steady State 7.5 9.5 thJC Notes: a. Package limited. b. Surface mounted on 1 x 1 FR4 board. c. t = 5 s. d. See solder profile (www.vishay.com/doc 73257). The PowerPAK SC-75 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 105 C/W. Document Number: 62821 For technical questions, contact: pmostechsupport vishay.com www.vishay.com S13-0197-Rev. A, 28-Jan-13 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000New Product SiB441EDK Vishay Siliconix SPECIFICATIONS (T = 25 C, unless otherwise noted) J Parameter Symbol Test Conditions Min.Typ.Max.Unit Static V V = 0 V, I = - 250 A Drain-Source Breakdown Voltage - 12 V DS GS D V Temperature Coefficient V /T - 5 DS DS J I = - 250 A mV/C D V Temperature Coefficient V /T 2.7 GS(th) GS(th) J V V = V , I = - 250 A Gate-Source Threshold Voltage - 0.4 - 0.9 V GS(th) DS GS D V = 0 V, V = 8 V 4 DS GS I Gate-Source Leakage GSS V = 0 V, V = 4.5 V 1 DS GS A V = - 12 V, V = 0 V - 1 DS GS I Zero Gate Voltage Drain Current DSS V = - 12 V, V = 0 V, T = 55 C - 10 DS GS J a I V - 5 V, V = - 4.5 V - 15 A On-State Drain Current D(on) DS GS V = - 4.5 V, I = - 4 A 0.0210 0.0255 GS D V = - 3.7 V, I = - 4 A 0.0230 0.0280 GS D a R V = - 2.5 V, I = - 2 A 0.0290 0.0360 Drain-Source On-State Resistance DS(on) GS D V = - 1.8 V, I = - 2 A 0.0420 0.0600 GS D V = - 1.5 V, I = - 0.5 A 0.0570 0.1150 GS D a g V = - 6 V, I = - 4 A 17 S Forward Transconductance fs DS D b Dynamic C Input Capacitance 1180 iss C V = - 6 V, V = 0 V, f = 1 MHz Output Capacitance 265 pF oss DS GS C Reverse Transfer Capacitance 250 rss V = - 6 V, V = - 8 V, I = - 2.1 A 22.1 33 DS GS D Q Total Gate Charge g 13.4 20 nC Q Gate-Source Charge V = - 6 V, V = - 4.5 V, I = - 2.1 A 1.6 gs DS GS D Q Gate-Drain Charge 3.4 gd Gate Resistance R f = 1 MHz 2.2 11 22 g t Turn-On Delay Time 22 45 d(on) Rise Time t 42 85 V = - 6 V, R = 2.7 r DD L I - 2.2 A, V = - 4.5 V, R = 1 t Turn-Off Delay Time D GEN g 60 120 d(off) Fall Time t 50 100 f ns t Turn-On Delay Time 715 d(on) Rise Time t 10 20 r V = - 6 V, R = 2.7 DD L I - 2.2 A, V = - 8 V, R = 1 t Turn-Off Delay Time D GEN g 60 120 d(off) t Fall Time 52 100 f Drain-Source Body Diode Characteristics I T = 25 C Continuous Source-Drain Diode Current - 9 S C A I Pulse Diode Forward Current - 40 SM V I = - 2.2 A, V = 0 V Body Diode Voltage - 0.85 - 1.2 V SD S GS t Body Diode Reverse Recovery Time 30 60 ns rr Body Diode Reverse Recovery Charge Q 12 25 nC rr I = - 2.2 A, dI/dt = 100 A/s, T = 25 C F J t Reverse Recovery Fall Time 9 a ns Reverse Recovery Rise Time t 11 b Notes: a. Pulse test pulse width 300 s, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 62821 For technical questions, contact: pmostechsupport vishay.com www.vishay.com S13-0197-Rev. A, 28-Jan-13 2 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000